Machine Learning Engineer - Chip Design Automation

Ixana is hiring a Machine Learning Engineer - Chip Design Automation in Bengaluru, India. The details below summarise the employer's own listing; applications happen on the original posting, not on GetFirstJob.

What the work involves

• Build predictive models for PPA Timing:
• Develop ML models to predict Power, Performance, Area, and timing violations critical paths, setup/hold slack at early RTL and synthesis stages to reduce costly signoff iterations
• Automate Physical Design:
• Apply Reinforcement Learning RL and Graph Neural Networks GNNs to automate and optimize placement, routing, and floorplanning
• Process Chip Data at Scale:
• Work directly with circuit netlist formats Verilog gate-level, LEF/DEF, SPEF, SDC, Liberty to build graph-based representations for ML consumption
• Deploy Closed-Loop ML:
• Integrate trained ML models as closed-loop plugins within industry EDA tool scripts e.g., Tcl plugins so your predictions actively drive and influence real-time design decisions
• Predict Manufacturability:
• Build DRC hotspot prediction models to catch lithography and design rule violations pre-tapeout

What they are looking for

• What Were Looking For
• 3-6 years of ML/AI engineering experience or exceptional academic background/Masters/PhD focused on ML for EDA
• Bachelors or Masters degree in Computer Science, Electrical Engineering, or a related field with a GPA of 9+ from IITs, NITs, BITS, or IISc
• Deep ML/AI Expertise: Strong proficiency in Python and deep learning frameworks PyTorch or TensorFlow , specifically with experience in graph-based ML GNNs, graph transformers on structured relational data
• EDA Data Fluency: Proven ability to parse and manipulate chip design data formats LEF/DEF, SPEF, SDC, Liberty, gate-level Verilog
• Automation Scripting: Advanced proficiency in scripting languages heavily used in EDA Tcl, Python, Perl, Bash
• End-to-End Ownership: Proven ability to take ML systems from data collection and training to inference and deployment
• Prior experience applying ML to EDA algorithms using data from commercial tools Synopsys, Cadence, or Siemens EDA

Pay and dates

The listed pay is Not Disclosed. The source page shows a relative posting age rather than an exact posting date; this role was first seen and checked as open on 4 November 2026. The source page showed it as posted “3+ weeks ago” when captured; that is a relative stamp, not an exact date.

How to apply

Apply on the listing where the employer published this role: Machine Learning Engineer - Chip Design Automation at Ixana. We found this listing via naukri.com; it was still open when we checked on 4 November 2026. If the posting has closed or the link fails, the role may have been filled.